| Presentation | 2002/2/25 kVerifier and SystemC Kenji Kobayashi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | kVerifier is a C++/STL library that verifies C/C++ program codes generally. I apply kVerifier to Reed Solomon ECC simulation and STL/valarray modeling and SystemC circuit discription. I exemplify that kVerifier and STL/valarray modeling is effective in system design and the examination, and that the test vector at system design is available for the RTL design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | CPSY2001-107 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2002/2/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | kVerifier and SystemC |
| Sub Title (in English) | |
| Keyword(1) | |
| 1st Author's Name | Kenji Kobayashi |
| 1st Author's Affiliation | () |
| Date | 2002/2/25 |
| Paper # | CPSY2001-107 |
| Volume (vol) | vol.101 |
| Number (no) | 671 |
| Page | pp.pp.- |
| #Pages | 7 |
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