Presentation	2001/4/6 Speculative Memory Access Mechanism for Thread-Level Speculation Makoto NAKAMURA, Kei HIRAKI,
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Abstract(in English)	To support efficiently speculative memory access fot thread-level speculation, we have proposed a cache mechanism without burst writeback when a speculation succeeds. The proposed mechanism maintains distributedly the ordering of speculative versions by using the binary relation, and resolves data dependencies by speculative forward. We have written a simulator for run-time loop restructuring method, and evaluated the performance. The loop construct of "swim" is executed three times faster by using four processors than sequential execution.
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Keyword(in English)	Thread-level speculation / speculative memory access / cache memory
Paper #	CPSY2001-11,FTS2001-11
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Conference Information
Committee	CPSY
Conference Date	2001/4/6(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Speculative Memory Access Mechanism for Thread-Level Speculation
Sub Title (in English)
Keyword(1)	Thread-level speculation
Keyword(2)	speculative memory access
Keyword(3)	cache memory
1st Author's Name	Makoto NAKAMURA
1st Author's Affiliation	Department of Information Science, Graduate School of Science, The University of Tokyo()
2nd Author's Name	Kei HIRAKI
2nd Author's Affiliation	Department of Information Science, Graduate School of Science, The University of Tokyo
Date	2001/4/6
Paper #	CPSY2001-11,FTS2001-11
Volume (vol)	vol.101
Number (no)	2
Page	pp.pp.-
#Pages	8
Date of Issue