| Presentation | 2001/4/6 A BIST Based on Concurrent Single-Control Testability of RTL Data Paths Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes new testability, concurrent single-control testability, of register transfer level data paths and a BIST(Buily-In Self Test) method for register transfer level data paths based on this testability. The proposed testability is extention of single-control testability and has advantage that test application time becomes shorter because multiple combinational modules can be tested at the same time (i.e., concurrent testing) The experimental results show that the proposed method reduces test application time without increasing so much hardware overhead compared with the previous method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | design for testability / RTL data path / built-in self test / single-control testability / hierarchical test / concurrent test |
| Paper # | CPSY2001-3,FTS2001-3 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2001/4/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A BIST Based on Concurrent Single-Control Testability of RTL Data Paths |
| Sub Title (in English) | |
| Keyword(1) | design for testability |
| Keyword(2) | RTL data path |
| Keyword(3) | built-in self test |
| Keyword(4) | single-control testability |
| Keyword(5) | hierarchical test |
| Keyword(6) | concurrent test |
| 1st Author's Name | Ken-ichi Yamaguchi |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Hiroki Wada |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Toshimitsu Masuzawa |
| 3rd Author's Affiliation | Graduate School of Engineering Science, Osaka University |
| 4th Author's Name | Hideo Fujiwara |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2001/4/6 |
| Paper # | CPSY2001-3,FTS2001-3 |
| Volume (vol) | vol.101 |
| Number (no) | 2 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |