Presentation 2000/7/26
CPSY2000-43 Evaluation of Realtime RISC Core Casablanca
Kiyofumi Tanaka, Takashi Matsumoto,
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Abstract(in English) We have extended general purpose RISC processor architecture and developed a new RISC core : Casablanca for realtime control. The core has current RISC architecture and additional register sets used for trap/interrupt processing and achieves fast trap execution by changing the register sets and reducing overheads to save/restore the contents of the registers. Moreover, several extended instructions (iuter-registersets instructions, cache line forced fill/update instructions, cache prefetch instruction, byte twisting instructions, etc.) support convenient programming and fast executition. In this paper, we show detailed reports of the simulated execution improved by changing the register-sets and using the extended instructions. Moreover, we show the implementation FPGA and the results of the actual running.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) RISC Core, SPARC, interrupt, cache line forced fill/upate, cache prefetch
Paper # CPSY2000-43
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Conference Information
Committee CPSY
Conference Date 2000/7/26(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) CPSY2000-43 Evaluation of Realtime RISC Core Casablanca
Sub Title (in English)
Keyword(1) RISC Core, SPARC, interrupt, cache line forced fill/upate, cache prefetch
1st Author's Name Kiyofumi Tanaka
1st Author's Affiliation Department of Information Science, Faculty of Science, University of Tokyo()
2nd Author's Name Takashi Matsumoto
2nd Author's Affiliation PRESTO, Japan Science and Technology Corporation
Date 2000/7/26
Paper # CPSY2000-43
Volume (vol) vol.100
Number (no) 248
Page pp.pp.-
#Pages 8
Date of Issue