Presentation	2000/4/21 Instruction fetch mechanism based on latency prediction Yutaka Sugawara, Kei Hiraki,
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Abstract(in English)	The performance of SMT (Simultaneous Multithreading)processor depends on thread selection algorithm used by instruction fetch unit. If instructions are fetched from inappropriate thread, the processor′s queue is occupied by instructions which can not be issued because of dependence, or the processor executes wrong path, and the throughput of the processor is decreased. Some thread selection methods have been proposed to improve processor′s throughput. These algorithms, however, do not use information of each instruction. In this paper, we propose a fetch mechanism whichuses instruction behavior information and performs more precise control. We examine the effectiveness of the mechanism by simulation. We found that the new algorithm improves processor′s throughput by 9.1% in maximum.
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Keyword(in English)	SMT / instruction fetch
Paper #	CPSY2000-2
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Conference Information
Committee	CPSY
Conference Date	2000/4/21(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Instruction fetch mechanism based on latency prediction
Sub Title (in English)
Keyword(1)	SMT
Keyword(2)	instruction fetch
1st Author's Name	Yutaka Sugawara
1st Author's Affiliation	Department of Information Science, Faculty of Science, University of Tokyo()
2nd Author's Name	Kei Hiraki
2nd Author's Affiliation	Department of Information Science, Faculty of Science, University of Tokyo
Date	2000/4/21
Paper #	CPSY2000-2
Volume (vol)	vol.100
Number (no)	20
Page	pp.pp.-
#Pages	8
Date of Issue