Presentation 1999/4/15
A Proposal of Chip-Sliced High-speed LSI for RSA Public-key Encryption.
Tsugio Nakamura, Tsutomu Saitou, Kazuhiro Abe, Hiroshi Kasahara,
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Abstract(in English) RSA encryption has been widely used as the practical standard of the public key cryptosystem for information security. In RSA encryption, the power residue arithmetic for numbers more than 1,024 bits and variable word length of the key is needed because of keeping the adequate security. For this reason, the technique for speeding up the arithmetic becomes more important. In this paper, we proposed a new arithmetic hardware with the repeated usage of single parallel multiplier/divider and its application to chip-sliced high-speed LSI for RSA encryption.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Public key encryption / RSA encryption / Chip slice / Information security / Residue arithmetic
Paper # CPSY99-2
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Conference Information
Committee CPSY
Conference Date 1999/4/15(1days)
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Paper Information
Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Proposal of Chip-Sliced High-speed LSI for RSA Public-key Encryption.
Sub Title (in English)
Keyword(1) Public key encryption
Keyword(2) RSA encryption
Keyword(3) Chip slice
Keyword(4) Information security
Keyword(5) Residue arithmetic
1st Author's Name Tsugio Nakamura
1st Author's Affiliation Kokusai Junior College()
2nd Author's Name Tsutomu Saitou
2nd Author's Affiliation Tokyo Denki University
3rd Author's Name Kazuhiro Abe
3rd Author's Affiliation Tokyo Denki University
4th Author's Name Hiroshi Kasahara
4th Author's Affiliation Tokyo Denki University
Date 1999/4/15
Paper # CPSY99-2
Volume (vol) vol.99
Number (no) 5
Page pp.pp.-
#Pages 8
Date of Issue