| Presentation | 1999/4/15 Potential of the High Frequency Operation of a Pipelined Cache Memory Kazutoshi UKAI, Yasushi HIBINO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a design and performance evaluation of a pipelined cache memory and its potential of the high frequency operation is discussed. The Multithreaded Ultra Pipelined Processor which processes a number of threads in parallel with time sharing fashion has been proposed and designed. This processor can shorten the clock cycle time of a stage by dividing the stages, so the number of pipeline stages is inevitably increased. In order to operate this processor efficiently, the pipelined cache which supplies instructions and data on the high frequency is indispensable. When introducing the pipelining to the cache mechanism, increase of the number of pipeline stages enables reduction of shorten a clock cycle time. However, the clock cycle time depends on the latest stage such as a memory-cell array. This research examines how high frequency operation is possible by pipelining. For this objective, the circuit of the cache is designed for every stage in detail, and evaluated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multithreaded Pipelined Processor / cache / pipeline / memory-cell array / high frequency operation |
| Paper # | CPSY99-1 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1999/4/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Potential of the High Frequency Operation of a Pipelined Cache Memory |
| Sub Title (in English) | |
| Keyword(1) | Multithreaded Pipelined Processor |
| Keyword(2) | cache |
| Keyword(3) | pipeline |
| Keyword(4) | memory-cell array |
| Keyword(5) | high frequency operation |
| 1st Author's Name | Kazutoshi UKAI |
| 1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology:(Present address) Currently Glory Co., Ltd.() |
| 2nd Author's Name | Yasushi HIBINO |
| 2nd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology |
| Date | 1999/4/15 |
| Paper # | CPSY99-1 |
| Volume (vol) | vol.99 |
| Number (no) | 5 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |