| Presentation | 1994/4/22 Weight Update Method for Neural Network LSI with Low Bit-Storage Synapses Tomohisa Kimura, Takeshi Shima, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A synapse weight bit accuracy is reduced for constructing a large scale neural network on a limited small chip size.This paper describes a novel learning method for a neural network LSI which has low bit-storage synapse weights.In this method,the number of synapses which are modified at each learning iteration is limited. Simulation results show a learning per-formance is improved by taking the method.This proposed method is applicable to an LSI which has low bit-storage synapse weights. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / LSI / Learning / Bit accuracy |
| Paper # | CPSY94-21,FTS94-21,ICD94-21 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1994/4/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Weight Update Method for Neural Network LSI with Low Bit-Storage Synapses |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | LSI |
| Keyword(3) | Learning |
| Keyword(4) | Bit accuracy |
| 1st Author's Name | Tomohisa Kimura |
| 1st Author's Affiliation | Toshiba Research and Development Center() |
| 2nd Author's Name | Takeshi Shima |
| 2nd Author's Affiliation | Toshiba Research and Development Center |
| Date | 1994/4/22 |
| Paper # | CPSY94-21,FTS94-21,ICD94-21 |
| Volume (vol) | vol.94 |
| Number (no) | 15 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |