Presentation 1994/7/23
A symmetric network topology for asymmetric parallel computation
Yo Nonomura, Shun-ichi Kurino, Yoshiaki Fukazawa,
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Abstract(in English) Massively parallel machines aim to realize high speed computing by using large numbers of processing elements,however,their efficiency deterioration by communication can not be ignored. Communication delay is one of the communication cost.Assuming that some of the input data for a PE are sent by communication from other,idle time may be inserted for waiting data at thePE.The more idle time is,the less computing.speed.One way to solve this problem is to construct a new network topology to operate other computation in the idle time.In this paper,we present a symmetric network topology in which asymmetric computer tree can be embedded, and its properties.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) network / fibonacci number / parallel processing / communication delay
Paper # CPSY94-50
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Committee CPSY
Conference Date 1994/7/23(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A symmetric network topology for asymmetric parallel computation
Sub Title (in English)
Keyword(1) network
Keyword(2) fibonacci number
Keyword(3) parallel processing
Keyword(4) communication delay
1st Author's Name Yo Nonomura
1st Author's Affiliation School of Science & Engineering,Waseda University()
2nd Author's Name Shun-ichi Kurino
2nd Author's Affiliation Media Laboratory,Nihon University
3rd Author's Name Yoshiaki Fukazawa
3rd Author's Affiliation School of Science & Engineering,Waseda University
Date 1994/7/23
Paper # CPSY94-50
Volume (vol) vol.94
Number (no) 164
Page pp.pp.-
#Pages 8
Date of Issue