| Presentation | 1998/10/16 Non-Precharged Bit-Line Sensing Scheme for High-Speed Low-Power DRAMs Takahiro Yokoyama, Yoshiharu Kato, Nobuyoshi Nakaya, Teruaki Maeda, Mitsuhiro Higashiho, Yasuhisa Sugo, Fumio Baba, Tooru Miyabo, Satoru Saito, Yoshihiro Takemae, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a "Non-Precharged Bit-line Sensing" (NPBS) scheme in which data access is performed without precharging bit-lines. This realizes both an improvement of random access speed and a reduction of power dissipation. Also, we propose a power reduction scheme for the memory system named "Initial Same Data Write" (ISDW). A test chip using 0.28um CMOS process technology has achieved 30ns random access cycle time, and refresh power has been reduced by 55%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / random access / power reduction / sense amplifier / NPBS scheme / ISDW scheme |
| Paper # | DSP98-103,ICD98-190,CPSY98-105 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1998/10/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Non-Precharged Bit-Line Sensing Scheme for High-Speed Low-Power DRAMs |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | random access |
| Keyword(3) | power reduction |
| Keyword(4) | sense amplifier |
| Keyword(5) | NPBS scheme |
| Keyword(6) | ISDW scheme |
| 1st Author's Name | Takahiro Yokoyama |
| 1st Author's Affiliation | Fujitsu VLSI Limited() |
| 2nd Author's Name | Yoshiharu Kato |
| 2nd Author's Affiliation | Fujitsu VLSI Limited |
| 3rd Author's Name | Nobuyoshi Nakaya |
| 3rd Author's Affiliation | Fujitsu VLSI Limited |
| 4th Author's Name | Teruaki Maeda |
| 4th Author's Affiliation | Fujitsu VLSI Limited |
| 5th Author's Name | Mitsuhiro Higashiho |
| 5th Author's Affiliation | Fujitsu VLSI Limited |
| 6th Author's Name | Yasuhisa Sugo |
| 6th Author's Affiliation | Fujitsu VLSI Limited |
| 7th Author's Name | Fumio Baba |
| 7th Author's Affiliation | Fujitsu VLSI Limited |
| 8th Author's Name | Tooru Miyabo |
| 8th Author's Affiliation | Fujitsu Limited |
| 9th Author's Name | Satoru Saito |
| 9th Author's Affiliation | Fujitsu Limited |
| 10th Author's Name | Yoshihiro Takemae |
| 10th Author's Affiliation | Fujitsu Limited |
| Date | 1998/10/16 |
| Paper # | DSP98-103,ICD98-190,CPSY98-105 |
| Volume (vol) | vol.98 |
| Number (no) | 323 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |