| Presentation | 1998/8/5 Dynamically Load Balancing Scheme Considering the Load Variation Speed for Massively Parallel Computers Atsushi NUNOME, Hiroaki HIRATA, Haruo NIIMI, Kiyoshi SHIBAYAMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a dynamically load balancing scheme to improve processor utilization on massively parallel computers. In our scheme, each of processing elements(PE's) has the load information of its neighbor PE's, and updates the information through the communication with its neighbor PE's. The load information does not include only the workload value, but also the growing speed of workload. A relatively overloaded PE casts a part of its workload in the direction of the less loaded or load-declining area of PE's. Furthermore, the load information of a PE can be attached to an interprocessor communication message for travelling through the interprocessor network to a far location of PE. This mechanism reduces the propagation latency of load information with low cost. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | dynamically load balancing / OS for massively parallel computers |
| Paper # | CPSY98-70 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1998/8/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamically Load Balancing Scheme Considering the Load Variation Speed for Massively Parallel Computers |
| Sub Title (in English) | |
| Keyword(1) | dynamically load balancing |
| Keyword(2) | OS for massively parallel computers |
| 1st Author's Name | Atsushi NUNOME |
| 1st Author's Affiliation | Dept.of Electronics and Information Science, Faculty of Engineering and Design, Kyoto Institute of Technology() |
| 2nd Author's Name | Hiroaki HIRATA |
| 2nd Author's Affiliation | Dept.of Electronics and Information Science, Faculty of Engineering and Design, Kyoto Institute of Technology |
| 3rd Author's Name | Haruo NIIMI |
| 3rd Author's Affiliation | Dept.of Information and Communication Sciences, Faculty of Engineering, Kyoto Sangyo University |
| 4th Author's Name | Kiyoshi SHIBAYAMA |
| 4th Author's Affiliation | Dept.of Electronics and Information Science, Faculty of Engineering and Design, Kyoto Institute of Technology |
| Date | 1998/8/5 |
| Paper # | CPSY98-70 |
| Volume (vol) | vol.98 |
| Number (no) | 234 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |