Presentation 1998/9/21
Function Modules for Video Decoding and Computer Graphics
Hideyuki FUJISHIMA, Yusuke TAKEMOTO, Tomokazu YONEDA, Takao ONOYE, Isao SHIRAKAWA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The present paper describes two hybrid VLSI modules dedicated to MPEG-4 natural/synthetic video decoding, which are to be incorporated into an MPEG-4 based media-processor. One is Matrix-Vector Multiplier, which can perform the matrix-vector multiplication both in the inverse discrete transform and in the geometrical transformation of three dimensional computer graphics. Another is Image Mapping Module, which can be used commonly for the motion compensation of natural video objects and for the texture mapping of synthetic video objects. The implementaion result shows that these modules have been integrated with the use of 440k and 110k transistors, respectively. Both modules can operate at 20MHz or less.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MPEG-4 / media-processor / inverse discrete cosine transform / geometrical transformation / texture mapping / motion compensation
Paper # VLD98-41,ICD98-144,CPSY98-78,FTS98-68
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Conference Information
Committee CPSY
Conference Date 1998/9/21(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Function Modules for Video Decoding and Computer Graphics
Sub Title (in English)
Keyword(1) MPEG-4
Keyword(2) media-processor
Keyword(3) inverse discrete cosine transform
Keyword(4) geometrical transformation
Keyword(5) texture mapping
Keyword(6) motion compensation
1st Author's Name Hideyuki FUJISHIMA
1st Author's Affiliation Dept. Information Systems Eng., Osaka University : Research & Development Laboratory Kyushu Matsushita Electric Co., Ltd.()
2nd Author's Name Yusuke TAKEMOTO
2nd Author's Affiliation Dept. Information Systems Eng., Osaka University
3rd Author's Name Tomokazu YONEDA
3rd Author's Affiliation Dept. Information Systems Eng., Osaka University
4th Author's Name Takao ONOYE
4th Author's Affiliation Dept. Information Systems Eng., Osaka University
5th Author's Name Isao SHIRAKAWA
5th Author's Affiliation Dept. Information Systems Eng., Osaka University
Date 1998/9/21
Paper # VLD98-41,ICD98-144,CPSY98-78,FTS98-68
Volume (vol) vol.98
Number (no) 290
Page pp.pp.-
#Pages 8
Date of Issue