| Presentation | 1998/12/10 Maxflow based Method for Enumerating Mincut Edges of Graph Modelled Logic Circuit Kengo Azegami, Atsushi Takahashi, Yoji Kajitani, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Maxflow mincut theorem based polynomial time computation complexity algorithm for enumerating mincut edges of the graph modelled logic circuits is described. Our algorithm transforms the given undirected hypergraph which shows the target logic circuit into a directed graph. Then, iteratively traverses and clusters the directed graph with our newly developed traversing rule. In this paper, we will give a theorem showing that our algorithm is applicable to any undirected hypergraph when the sources and sinks are given. We will also show an example application in field of circuit bipartitioning which gives the largest possible subcircuit within the given size constraint. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Circuit Partitioning / Maxflow-Mincut theorem |
| Paper # | VLD98-116, CPSY98-136 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1998/12/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Maxflow based Method for Enumerating Mincut Edges of Graph Modelled Logic Circuit |
| Sub Title (in English) | |
| Keyword(1) | Circuit Partitioning |
| Keyword(2) | Maxflow-Mincut theorem |
| 1st Author's Name | Kengo Azegami |
| 1st Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech.() |
| 2nd Author's Name | Atsushi Takahashi |
| 2nd Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. |
| 3rd Author's Name | Yoji Kajitani |
| 3rd Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. |
| Date | 1998/12/10 |
| Paper # | VLD98-116, CPSY98-136 |
| Volume (vol) | vol.98 |
| Number (no) | 448 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |