Presentation 1998/4/24
Asynchronous Cascade ALU Architecture
Yoichiro UENO, Izumi Fukasaku, Hiroshi NAKAMURA, Takashi NANYA,
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Abstract(in English) In this paper, we propose an original asynchronous procesor architecture, Cascade ALU Architecture, for full utilization of multiple ALUs. While the superscalar and VLIW architectures can issue and execute only the instructions simultaneously that are independent with each other, the proposed architecture is able to issue and execute not only independent but also data-dependent instructions simultaneously by making the best use of asynchronous system features.
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Keyword(in English) Processor Architecture / Asynchronous processor / Super Scalar / VLIW
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Committee CPSY
Conference Date 1998/4/24(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Asynchronous Cascade ALU Architecture
Sub Title (in English)
Keyword(1) Processor Architecture
Keyword(2) Asynchronous processor
Keyword(3) Super Scalar
Keyword(4) VLIW
1st Author's Name Yoichiro UENO
1st Author's Affiliation Graduate School of Information Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name Izumi Fukasaku
2nd Author's Affiliation Graduate School of Information Science and Engineering, Tokyo Institute of Technology
3rd Author's Name Hiroshi NAKAMURA
3rd Author's Affiliation Research Center for Advanced Science and Technology, Tokyo University
4th Author's Name Takashi NANYA
4th Author's Affiliation Research Center for Advanced Science and Technology, Tokyo University
Date 1998/4/24
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Volume (vol) vol.98
Number (no) 25
Page pp.pp.-
#Pages 8
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