Presentation | 1995/6/23 Instruction Set Architecture of a Massively Parallel Computer RWC-1 Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Takashi Yokota, Shuichi Sakai, |
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Abstract(in English) | We have proposed a high-performance processor architecture RICA (Reduced Interprocessor-Communication Architecture), which decreases communication overhead by fusing thread execution and communication. Massively parallel Computer RWC-1 which consists of 1,024 PEs is now under construction. RWC-1 processor based on the RICA optimizes a local execution within a thread by super-scalar, and also optimizes a global execution among threads by decreasing communication and synchronization overheads with low cost hardware. This paper describes the instruction set architecture of the RWC-1 processor. It also presents how local execution and global execution are optimized. |
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Committee | CPSY |
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Conference Date | 1995/6/23(1days) |
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Registration To | Computer Systems (CPSY) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
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Title (in English) | Instruction Set Architecture of a Massively Parallel Computer RWC-1 |
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1st Author's Name | Kazuaki Okamoto |
1st Author's Affiliation | Tsukuba Research Center, Real World Computing Partnership() |
2nd Author's Name | Hiroshi Matsuoka |
2nd Author's Affiliation | Tsukuba Research Center, Real World Computing Partnership |
3rd Author's Name | Hideo Hirono |
3rd Author's Affiliation | Tsukuba Research Center, Real World Computing Partnership |
4th Author's Name | Takashi Yokota |
4th Author's Affiliation | Tsukuba Research Center, Real World Computing Partnership |
5th Author's Name | Shuichi Sakai |
5th Author's Affiliation | Tsukuba Research Center, Real World Computing Partnership |
Date | 1995/6/23 |
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Volume (vol) | vol.95 |
Number (no) | 125 |
Page | pp.pp.- |
#Pages | 6 |
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