Presentation 1995/4/28
A Hierarchical Parallel Processing Scheme of Circuit Simulation
Y. Maekawa, M. Takai, T. Itoh, T. Nishikawa, H. Kasahara,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper describes a hierarchical parallel processing scheme of circuit simulation using circuit tearing and near fine grain parallel processing. Parallel processing schemes of a circuit simulation using the circuit tearing has been often employed for circuit simulation systems. However, in the circuit tearing, there is a problem that it is difficult to tear a circuit to the same number of processors when a much processor is getting larger. Then, this paper proposes a hierarchical parallel processing scheme, which combines coarse grain parallel processing using circuit tearing and near fine grain processing inside the torn circuit. Also, performance of the proposed scheme is evaluated on a multiprocessor system OSCAR.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Circuit Simulation / Circuit Tearing / Hirarchical Parallel Processing / Static Scheduling / Loop Free Code
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Committee CPSY
Conference Date 1995/4/28(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hierarchical Parallel Processing Scheme of Circuit Simulation
Sub Title (in English)
Keyword(1) Circuit Simulation
Keyword(2) Circuit Tearing
Keyword(3) Hirarchical Parallel Processing
Keyword(4) Static Scheduling
Keyword(5) Loop Free Code
1st Author's Name Y. Maekawa
1st Author's Affiliation School of Science and Engineering, Waseda University()
2nd Author's Name M. Takai
2nd Author's Affiliation School of Science and Engineering, Waseda University
3rd Author's Name T. Itoh
3rd Author's Affiliation School of Science and Engineering, Waseda University
4th Author's Name T. Nishikawa
4th Author's Affiliation School of Science and Engineering, Waseda University
5th Author's Name H. Kasahara
5th Author's Affiliation School of Science and Engineering, Waseda University
Date 1995/4/28
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Volume (vol) vol.95
Number (no) 21
Page pp.pp.-
#Pages 8
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