Presentation 1995/4/28
Architecture for massively parallel processing vision chip
Takashi Komuro, Shinsuke Suzuki, Masatoshi Ishikawa,
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Abstract(in English) A new architecture for programmable parallel processing vision chip which has general purpose processing elements (PEs) with photo detectors has been designed and evaluated. As a result of simplifying its structure it is shown by simulation that the visionchip based on our architecture consists of only 700 transistors per each PE and can implement various early visual processing algorithms at the sampling rate of 1000frames/s.
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Keyword(in English) vision chip / parallel processing / early visual processing / VLSI
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Conference Information
Committee CPSY
Conference Date 1995/4/28(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Architecture for massively parallel processing vision chip
Sub Title (in English)
Keyword(1) vision chip
Keyword(2) parallel processing
Keyword(3) early visual processing
Keyword(4) VLSI
1st Author's Name Takashi Komuro
1st Author's Affiliation Department of Mathematical Engineering and Information Physics, Faculty of Engineering, University of Tokyo()
2nd Author's Name Shinsuke Suzuki
2nd Author's Affiliation Department of Mathematical Engineering and Information Physics, Faculty of Engineering, University of Tokyo
3rd Author's Name Masatoshi Ishikawa
3rd Author's Affiliation Department of Mathematical Engineering and Information Physics, Faculty of Engineering, University of Tokyo
Date 1995/4/28
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Volume (vol) vol.95
Number (no) 21
Page pp.pp.-
#Pages 7
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