Presentation 1995/4/28
Processor Chip Design for the Massively Parallel Computer RWC-1
Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Takashi Yokota, Shuichi Sakai,
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Abstract(in English) One of the most important issues on parallel computing is how to decrease the communication overhead. On design concepts, the massively parallel computer RWC-1 adopts the RICA(Reduced Inter-processor Communication Architecture) to considerably decrease communication overhead with low hardware cost, and provides OS support facilities to realize data protection against illegal procedure. In this paper, the authors report the first implementation of the processor chip for the massively parallel computer RWC-1, and discuss it's efficiency.
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Keyword(in English) massively parallel computing / processor architecture / multi-treaded execution / RICA
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Committee CPSY
Conference Date 1995/4/28(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Processor Chip Design for the Massively Parallel Computer RWC-1
Sub Title (in English)
Keyword(1) massively parallel computing
Keyword(2) processor architecture
Keyword(3) multi-treaded execution
Keyword(4) RICA
1st Author's Name Hiroshi Matsuoka
1st Author's Affiliation Tsukuba Research Center, Real World Computing Partnership()
2nd Author's Name Kazuaki Okamoto
2nd Author's Affiliation Tsukuba Research Center, Real World Computing Partnership
3rd Author's Name Hideo Hirono
3rd Author's Affiliation Tsukuba Research Center, Real World Computing Partnership
4th Author's Name Takashi Yokota
4th Author's Affiliation Tsukuba Research Center, Real World Computing Partnership
5th Author's Name Shuichi Sakai
5th Author's Affiliation Tsukuba Research Center, Real World Computing Partnership
Date 1995/4/28
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Volume (vol) vol.95
Number (no) 21
Page pp.pp.-
#Pages 8
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