Presentation 1995/4/28
A Cache Memory System for On-chip Multiprocessor
T. Terasawa, K. Inoue, H. Kurosawa, H. Amano,
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Abstract(in English) Considering recent improvement of VLSI technology, bus-connected multiprocessors will be implemented on a single chip within several years. In this paper, we propose a snoop cache system for this on-chip multiprocessor. It supports an enhanced ownership mechanism and two types of cache coherency protocols for minimizing off-chip data transfer. It also includes mechanisms for synchronization without off-chip communications. Instruction level simulations demonstrate that our cache achieves higher performance than existing cache memories. We also describe on a prototype machine ATTEMPT-1 which will be used for detailed evaluation of the protocol.
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Keyword(in English) Multiprocessor Chip / Snoop Cache Protocol / Instruction Level Simulator
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Committee CPSY
Conference Date 1995/4/28(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Cache Memory System for On-chip Multiprocessor
Sub Title (in English)
Keyword(1) Multiprocessor Chip
Keyword(2) Snoop Cache Protocol
Keyword(3) Instruction Level Simulator
1st Author's Name T. Terasawa
1st Author's Affiliation Tokyo Engineering University()
2nd Author's Name K. Inoue
2nd Author's Affiliation Keio University
3rd Author's Name H. Kurosawa
3rd Author's Affiliation Keio University
4th Author's Name H. Amano
4th Author's Affiliation Keio University
Date 1995/4/28
Paper #
Volume (vol) vol.95
Number (no) 21
Page pp.pp.-
#Pages 8
Date of Issue