| Presentation | 1995/4/28 A Speedup Technique for Concurrent Fault Simulation Using the One-pass Event-driven Strategy Eiji Harada, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Fault simulation is currently considered one of the most time-consuming processes for circuit designs. Although there have been a lot of fault simulation techniques proposed, the orders of growth on those are almost the same. So, this has motivated the use of hierarchical design info. and parallel processing. This paper focused on the concurrent fault simulation method, which is the most appropriate when expanding to hierarchical fault simulation, and presents a speedup technique for the method using the one-pass event-driven simulation strategy, and also presents some experimental results using the ISCAS benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
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| Committee | CPSY |
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| Conference Date | 1995/4/28(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Speedup Technique for Concurrent Fault Simulation Using the One-pass Event-driven Strategy |
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| 1st Author's Name | Eiji Harada |
| 1st Author's Affiliation | ULSI Systems Development Laboratories NEC Corporation() |
| Date | 1995/4/28 |
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| Volume (vol) | vol.95 |
| Number (no) | 21 |
| Page | pp.pp.- |
| #Pages | 7 |
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