| Presentation | 1995/4/28 A Method of Performance Driven Layout for Asynchronous Circuits Akihiro Takamura, Taro Fujii, Takashi Nanya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The speed of asynchronous circuits are limited by the average delay of sensitizable paths. In this paper, we present a method of performance driven layout for asynchronous circuits. This method determines the layout priorities of the wires according to the expectation of the signal transitions in sensitizable paths. The performance of the asynchronous processor TITAC-1 could be improved about 20% by using a logic simulator to find out the sensitizable paths and determining the priority of the wires with this method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asynchronous circuit / performance driven layout / request-acknowledge model / sensitizable path |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1995/4/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of Performance Driven Layout for Asynchronous Circuits |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuit |
| Keyword(2) | performance driven layout |
| Keyword(3) | request-acknowledge model |
| Keyword(4) | sensitizable path |
| 1st Author's Name | Akihiro Takamura |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Taro Fujii |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology |
| 3rd Author's Name | Takashi Nanya |
| 3rd Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology |
| Date | 1995/4/28 |
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| Volume (vol) | vol.95 |
| Number (no) | 21 |
| Page | pp.pp.- |
| #Pages | 6 |
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