Presentation 1995/4/27
Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment
K. Kotani, T. Shibata, M. Imai, T. Ohmi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A new clocked circuit scheme has been developed for Neuron MOS (νMOS) logic circuits, resulting in significantly enhanced noise margins by an auto-threshold-adjustment capability. In addition, the functionality of a νMOS gate is further enhanced by the gate-level data subtraction. Low-power operation is achieved by the logic decision using a sense-amplifier in the architecture of the pipelined νMOS logic-gate.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) neuron-MOS transistor / logic circuit / Clock signal / sense amplifier
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Committee CPSY
Conference Date 1995/4/27(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment
Sub Title (in English)
Keyword(1) neuron-MOS transistor
Keyword(2) logic circuit
Keyword(3) Clock signal
Keyword(4) sense amplifier
1st Author's Name K. Kotani
1st Author's Affiliation Department of Electronics, Tohoku University:Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University()
2nd Author's Name T. Shibata
2nd Author's Affiliation Department of Electronics, Tohoku University
3rd Author's Name M. Imai
3rd Author's Affiliation Department of Electronics, Tohoku University
4th Author's Name T. Ohmi
4th Author's Affiliation Department of Electronics, Tohoku University
Date 1995/4/27
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Volume (vol) vol.95
Number (no) 20
Page pp.pp.-
#Pages 8
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