| Presentation | 1995/4/27 Reconfigurable Parallel VLSI Processor Based on Bit-Serial Architecture and Its Application to Intelligent Integrated Systems Yoshinori Ueno, Yoshichika Fujioka, Michitaka Kameyama, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the sensor feedback control of intelligent systems, the delay time must be reduced for a large number of arithmetic operations. To reduce the delay time for arithmetic operations, the architecture of the reconfigurable parallel VLSI processor is proposed. In each processor element (PE), a switch circuit is used to change the connection between the multipliers and adders, so that the arithmetic circuits can be reconfigured. However, the interconnection delay is large in bit-parallel architecture. To reduce the interconnection delay, a reconfigurable parallel VLSI processor based on bit-serial architecture is proposed. The performance evaluation shows that the delay time inverse dynamics computation of a six-degrees-of-freedom manipulator becomes about 1.25 times smaller than that of a reconfigurable parallel VLSI processor based on bit-parallel architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | small delay time / intelligent integrated system / multi-operand multiply-addition / bit-serial architecture / reconfigurable parallel architecture |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1995/4/27(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reconfigurable Parallel VLSI Processor Based on Bit-Serial Architecture and Its Application to Intelligent Integrated Systems |
| Sub Title (in English) | |
| Keyword(1) | small delay time |
| Keyword(2) | intelligent integrated system |
| Keyword(3) | multi-operand multiply-addition |
| Keyword(4) | bit-serial architecture |
| Keyword(5) | reconfigurable parallel architecture |
| 1st Author's Name | Yoshinori Ueno |
| 1st Author's Affiliation | Graduate School of Information Sciences Tohoku University() |
| 2nd Author's Name | Yoshichika Fujioka |
| 2nd Author's Affiliation | Department of Electrical Engineering Hachinohe Institute of Technology |
| 3rd Author's Name | Michitaka Kameyama |
| 3rd Author's Affiliation | Graduate School of Information Sciences Tohoku University |
| Date | 1995/4/27 |
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| Volume (vol) | vol.95 |
| Number (no) | 20 |
| Page | pp.pp.- |
| #Pages | 7 |
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