| Presentation | 1995/4/27 1.5-V Source-Coupled Current-Mode Multiple-Valued Integrated Circuits and Its Application to a High-Speed Pipelined Multiplier Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents the design of a multiple-valued current-mode(MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation. A dual-rail source-coupled logic circuit is used as a basic component to make a signal-voltage swing small with keeping a large driving capability. Moreover, the pipeline architecture is suitable for efficiently employing the proposed MVCM logic circuits in high-speed arithmetic operations. The latched source-coupled logic circuits for the pipeline architecture can be simply designed by inserting two CMOS pass transistors at the gates of the source-coupled transistors. As a result, the operating speed of a 54-bit pipelined multiplier using the proposed MVCM logic circuits is evaluated to be 1.4 times faster than that of the corresponding binary implementation under the same power dissipation and the supply voltage of 1.5V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | current-mode multiple-valued integrated circuit / threshold detector / dual-rail complementary signal / source-coupled circuit / signed-digit adder / pipelined multiplier |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1995/4/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1.5-V Source-Coupled Current-Mode Multiple-Valued Integrated Circuits and Its Application to a High-Speed Pipelined Multiplier |
| Sub Title (in English) | |
| Keyword(1) | current-mode multiple-valued integrated circuit |
| Keyword(2) | threshold detector |
| Keyword(3) | dual-rail complementary signal |
| Keyword(4) | source-coupled circuit |
| Keyword(5) | signed-digit adder |
| Keyword(6) | pipelined multiplier |
| 1st Author's Name | Takahiro Hanyu |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Akira Mochizuki |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka Kameyama |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 1995/4/27 |
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| Volume (vol) | vol.95 |
| Number (no) | 20 |
| Page | pp.pp.- |
| #Pages | 7 |
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