Presentation | 1995/4/27 Performance Evaluation of GHz-Class RISC Pipeline Architecture Emi Kaneko, Masafumi Takahashi, Haruyuki Tago, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A performance of GHz-class RISC pipeline architecture has been simulated with benchmark -SPECint92-. 2GHz-clock with fifteen stages pipeline model operates 10 to 14 times faster than four stages pipeline model (50MHz), 4 to 5 times than R4000 model (200MHz). Because of increase of stall clocks due to data dependency and NOPs in delay slots, it does not mark full performance proportional to its clock frequency. Enhancements of compiler optimization is necessary. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | RISC / pipeline / compiler / latency / ALU |
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Committee | CPSY |
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Conference Date | 1995/4/27(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Computer Systems (CPSY) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Performance Evaluation of GHz-Class RISC Pipeline Architecture |
Sub Title (in English) | |
Keyword(1) | RISC |
Keyword(2) | pipeline |
Keyword(3) | compiler |
Keyword(4) | latency |
Keyword(5) | ALU |
1st Author's Name | Emi Kaneko |
1st Author's Affiliation | Research and Development Center, Toshiba Corp.() |
2nd Author's Name | Masafumi Takahashi |
2nd Author's Affiliation | Research and Development Center, Toshiba Corp. |
3rd Author's Name | Haruyuki Tago |
3rd Author's Affiliation | Research and Development Center, Toshiba Corp. |
Date | 1995/4/27 |
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Volume (vol) | vol.95 |
Number (no) | 20 |
Page | pp.pp.- |
#Pages | 8 |
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