| Presentation | 1994/1/25 Evaluation of a Cache Memory with a prefetch Mechanism for High Performance Processors Masafumi Takahashi, Takeshi Yoshida, Toshinori Sato, Hiroyuki Takano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A cache architecture with a prefetch mechanism has been simulated,which has been studied for high speed processors that run at over 250-MHz and a high speed DRAM such as Rambus DRAM or synchronous DRAM.As a result,a model with prefetch operates 1.2 to 1.8 times faster than a model without prefetch at 250-MHz clock rate when the Rambus DRAM is connected.The optimized D-cache organization,which includes the prefetch buffer size,the write- back buffer size,and the line size of the cache,depends on the application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cache memory / prefetch / prefetch buffer / write back buffer / Rombus |
| Paper # | CPSY93-49 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1994/1/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of a Cache Memory with a prefetch Mechanism for High Performance Processors |
| Sub Title (in English) | |
| Keyword(1) | cache memory |
| Keyword(2) | prefetch |
| Keyword(3) | prefetch buffer |
| Keyword(4) | write back buffer |
| Keyword(5) | Rombus |
| 1st Author's Name | Masafumi Takahashi |
| 1st Author's Affiliation | Research and Development Center,Toshiba Corporation() |
| 2nd Author's Name | Takeshi Yoshida |
| 2nd Author's Affiliation | Research and Development Center,Toshiba Corporation |
| 3rd Author's Name | Toshinori Sato |
| 3rd Author's Affiliation | Research and Development Center,Toshiba Corporation |
| 4th Author's Name | Hiroyuki Takano |
| 4th Author's Affiliation | Research and Development Center,Toshiba Corporation |
| Date | 1994/1/25 |
| Paper # | CPSY93-49 |
| Volume (vol) | vol.93 |
| Number (no) | 436 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |