Presentation 1993/8/19
An implementation and performance evaluation of SNAIL:a multiprocessor based on the SSS-MIN
Masashi Sasahara, Jun Terada, Junichi Yamato, Hideharu Amano,
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Abstract(in English) Simple Serial Synchronized(SSS)Multistage Interconnection Network(MIN)is a novel MIN architecture for connecting processors and memory modules in multiprocessors.Synchronized bit-serial communication simplifies the structure, control,and also solves the pin-limitation problem.The simple structure allows the use of a high frequency clock rate and a high throughput network topology. An LSI implementation of the SSS-MIN has been completed. Using these chips,a multiprocessor prototype called SNAIL with 16 processors, 16 memory modules is under development,and a system with 4 processors/4 memory modules is operational.The small overhead of the SSS-MIN is demonstrated with some parallel benchmark programs.The performance enhancement mechanisms such as data prefetch and message combining are also evaluated.
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Keyword(in English) multiprocessor / MIN / performance evaluation
Paper # CPSY93-29
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Committee CPSY
Conference Date 1993/8/19(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An implementation and performance evaluation of SNAIL:a multiprocessor based on the SSS-MIN
Sub Title (in English)
Keyword(1) multiprocessor
Keyword(2) MIN
Keyword(3) performance evaluation
1st Author's Name Masashi Sasahara
1st Author's Affiliation Faculty of Science and Technology,Keio University()
2nd Author's Name Jun Terada
2nd Author's Affiliation Faculty of Science and Technology,Keio University
3rd Author's Name Junichi Yamato
3rd Author's Affiliation Faculty of Science and Technology,Keio University
4th Author's Name Hideharu Amano
4th Author's Affiliation Faculty of Science and Technology,Keio University
Date 1993/8/19
Paper # CPSY93-29
Volume (vol) vol.93
Number (no) 181
Page pp.pp.-
#Pages 8
Date of Issue