Presentation 1993/8/19
Evaluation of Communication System for Parallel Inference Engine PIE64
Mitsuru Sato, Hanpei Koike, Hidehiko Tanaka,
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Abstract(in English) The current key for successful high-performance computing requires creating massively parallel computers.When we develop a massively parallel computer,we must consider interconnection networks.It is because the communication and the synchronization among the processing elements are important.Tey have been well studied theoretically without actual costs.They do not apply the evaluation the latency hiding techniques to the evaluations.The technique of overlapping communication and calculation is influential for gaining high performance.The constraint and the demand for interconnection networks may be changed,if we evaluate them with the technique.We construct a simulator with the facilities to change and evaluate the networks.We run the application codes using optimization techniques for static latency hiding and evaluate the interconnection network topology.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Evaluation / Communication System / Parallel Computer
Paper # CPSY93-28
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Committee CPSY
Conference Date 1993/8/19(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of Communication System for Parallel Inference Engine PIE64
Sub Title (in English)
Keyword(1) Evaluation
Keyword(2) Communication System
Keyword(3) Parallel Computer
1st Author's Name Mitsuru Sato
1st Author's Affiliation Faculty of Engineering,University of Tokyo()
2nd Author's Name Hanpei Koike
2nd Author's Affiliation Faculty of Engineering,University of Tokyo
3rd Author's Name Hidehiko Tanaka
3rd Author's Affiliation Faculty of Engineering,University of Tokyo
Date 1993/8/19
Paper # CPSY93-28
Volume (vol) vol.93
Number (no) 181
Page pp.pp.-
#Pages 8
Date of Issue