| Presentation | 1996/8/26 Virtual Network Schemes for Shared-Memory Multiprocessors Masaru Takesue, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes schemes for efficient virtual networks on large-scale shared-memory multiprocessors. With the conventional cache coherence protocol, communication especially between neighboring nodes of the virtual network suffers a great amount of performance degradation from the cache coherence operations. To alleviate that degradation, a tampering cache coherence protocol and a stream buffer are introduced. The tampering cache protocol can freeze a memory block into a cache. All requests to the frozen block are redirected to the freezing cache, that accesses the copy of frozen block with no invalidation. The stream buffer synchronizes the read and write accesses to a stream variable allocated in the frozen block. The size of the stream buffer is proportional to the size of cache. The simulation result shows that communication latency, (data-miss ratio)×(miss penalty), of the virtual mesh with the tampering cache protocol is about 0.14 times that of the naive virtual mesh without that protocol. The virtual mesh with both the tampering protocol and stream buffer has about 0.06 times the latency of naive virtual mesh. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Virtual networks / shared-memory multiprocessors / cache coherence protocols / communication latency / synchronization |
| Paper # | CPSY-96-51 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1996/8/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Virtual Network Schemes for Shared-Memory Multiprocessors |
| Sub Title (in English) | |
| Keyword(1) | Virtual networks |
| Keyword(2) | shared-memory multiprocessors |
| Keyword(3) | cache coherence protocols |
| Keyword(4) | communication latency |
| Keyword(5) | synchronization |
| 1st Author's Name | Masaru Takesue |
| 1st Author's Affiliation | Department of Electronics and Information Engineering, Hosei University() |
| Date | 1996/8/26 |
| Paper # | CPSY-96-51 |
| Volume (vol) | vol.96 |
| Number (no) | 230 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |