| Presentation | 1996/8/26 ATTEMPT-1 : A reconfigurable testbed for multiprocessor-chip M. Okuno, K. Inoue, T. Kisuki, K. Kimura, T. Terasawa, H. Amano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | ATTEMPT-1 is a reconfigurable testbed proposed to emulate cache systems for future multiprocessors which will be implemented on an LS1 chip. It has a highly flexible environment, to evaluate cache by using programmable devices (FPGA and CPLD). The cache controller, bus controller and performance monitor are implemented with SRAM CPLD. By rewriting the HDL description, cache protocol, bus operation speed and other issues on cache/memory system can be changed. On the other hand, cache datapath which requires quick operation is implemented with anti-fuse FPGA. Cache size, line size and the number of ways can be flexibly selected without degrading the performance. The various design trade-off on multiprocessor chip can be easily evaluated with this flexible structure of ATTEMPT-1. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multiprocessor-chip Performance evaluation / Reconfigurable testbed / FPGA/CPLD / HDL |
| Paper # | CPSY-96-48 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1996/8/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ATTEMPT-1 : A reconfigurable testbed for multiprocessor-chip |
| Sub Title (in English) | |
| Keyword(1) | Multiprocessor-chip Performance evaluation |
| Keyword(2) | Reconfigurable testbed |
| Keyword(3) | FPGA/CPLD |
| Keyword(4) | HDL |
| 1st Author's Name | M. Okuno |
| 1st Author's Affiliation | Keio University() |
| 2nd Author's Name | K. Inoue |
| 2nd Author's Affiliation | Keio University |
| 3rd Author's Name | T. Kisuki |
| 3rd Author's Affiliation | Keio University |
| 4th Author's Name | K. Kimura |
| 4th Author's Affiliation | Keio University |
| 5th Author's Name | T. Terasawa |
| 5th Author's Affiliation | Tokyo Engineering University |
| 6th Author's Name | H. Amano |
| 6th Author's Affiliation | Keio University |
| Date | 1996/8/26 |
| Paper # | CPSY-96-48 |
| Volume (vol) | vol.96 |
| Number (no) | 230 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |