| Presentation | 1997/3/19 Preliminary performance evaluation of the interconnection network of the real-time paralle1 system CODA Kenji TODA, Kenji NISHIDA, Eiichi TAKAHASHI, Yoshinori YAMAGUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 4 by 4 router chip, which facilitates 32-bit priority arbitration by mean of a proposed priority forwarding scheme in order to prevent priority inversion, has been fabricated and embedded in the real-time parallel processor CODA. The CODA is capable of having 64 processors connected by 48 router chips of reverse baseline network. Currently sixteen-processor sub-system where a processor is implemented by a FPGA is operational. This manuscript describes the specification of the router chip and evaluation status of the network using the FPGA-processor system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Priority Forwarding Scheme / Real-Tinle Interconnection Network / Priority Queue / Real-Time Parallel Architecture / Router Chip / Performance Evaluation / FPGA |
| Paper # | CPSY96-118 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1997/3/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Preliminary performance evaluation of the interconnection network of the real-time paralle1 system CODA |
| Sub Title (in English) | |
| Keyword(1) | Priority Forwarding Scheme |
| Keyword(2) | Real-Tinle Interconnection Network |
| Keyword(3) | Priority Queue |
| Keyword(4) | Real-Time Parallel Architecture |
| Keyword(5) | Router Chip |
| Keyword(6) | Performance Evaluation |
| Keyword(7) | FPGA |
| 1st Author's Name | Kenji TODA |
| 1st Author's Affiliation | Electrotechnical Laboratory() |
| 2nd Author's Name | Kenji NISHIDA |
| 2nd Author's Affiliation | Electrotechnical Laboratory |
| 3rd Author's Name | Eiichi TAKAHASHI |
| 3rd Author's Affiliation | Electrotechnical Laboratory |
| 4th Author's Name | Yoshinori YAMAGUCHI |
| 4th Author's Affiliation | Electrotechnical Laboratory |
| Date | 1997/3/19 |
| Paper # | CPSY96-118 |
| Volume (vol) | vol.96 |
| Number (no) | 597 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |