Presentation 1998/1/30
The Evaluation of MBP Core Architecture for A Massively Parallel Machine-JUMP-1
Hiroaki Inoue, Ken-ichiro Anjo, Mitsuru Sato, Takashi Fujiwara, Tsuyoshi Abe, Hideharu Amano,
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Abstract(in English) A massively parallel machine JUMP-1 has been developed for building an efficient cache coherent-distributed shared memory on a large system with more than 1000 processors. In this paper, we evaluate a dedicated simple processor architecture called Buffer-Register Architecture adopted in the MBP (Memory Based Processor)-light which manages the distributed shared memory on JUMP-1. Compared with a simple common 32bit RISC processor, it can manage the distributed shared memory quickly with a small amount of hardware.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) JUMP-1 / MBP-light / Buffer-Register Architecture
Paper # CPSY97-101
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Conference Information
Committee CPSY
Conference Date 1998/1/30(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The Evaluation of MBP Core Architecture for A Massively Parallel Machine-JUMP-1
Sub Title (in English)
Keyword(1) JUMP-1
Keyword(2) MBP-light
Keyword(3) Buffer-Register Architecture
1st Author's Name Hiroaki Inoue
1st Author's Affiliation Keio University()
2nd Author's Name Ken-ichiro Anjo
2nd Author's Affiliation Keio University
3rd Author's Name Mitsuru Sato
3rd Author's Affiliation Fujitsu Laboratories LTD
4th Author's Name Takashi Fujiwara
4th Author's Affiliation Keio University
5th Author's Name Tsuyoshi Abe
5th Author's Affiliation Keio University
6th Author's Name Hideharu Amano
6th Author's Affiliation Keio University
Date 1998/1/30
Paper # CPSY97-101
Volume (vol) vol.97
Number (no) 524
Page pp.pp.-
#Pages 8
Date of Issue