| Presentation | 1997/12/12 A Consideration on Pass Transistor Logic Circuit Design by a BDD Decomposition Hidekazu Kanaya, Shuji Tsukiyama, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Pass transistor logic circuits draw attention as low power circuits, and also show good performance in speed for some practical circuits. In this paper, we consider an algorithm to realize a given shared BDD with plural outputs as a multiple pass transistor circuits, by decomposing the shared BDD. When realizing, the total number of transistors and the maximum delay are to be minimized. So far, only the number of series pass transistors or the pass transistors connected through source and drain are taken into consideration for the maximum delay. But, it is necessary to take the delay through a gate of a pass transistor into consideration in the proposed pass transistor circuit design. This paper proposes an algorithm for estimating such a delay. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Pass Transistor Logic Circuit / Delay Estimation / Shared BDD / Decomposition by QRBDD |
| Paper # | CPSY97-94 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1997/12/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Consideration on Pass Transistor Logic Circuit Design by a BDD Decomposition |
| Sub Title (in English) | |
| Keyword(1) | Pass Transistor Logic Circuit |
| Keyword(2) | Delay Estimation |
| Keyword(3) | Shared BDD |
| Keyword(4) | Decomposition by QRBDD |
| 1st Author's Name | Hidekazu Kanaya |
| 1st Author's Affiliation | Department of Electrical and Electronic Engineering Chuo University() |
| 2nd Author's Name | Shuji Tsukiyama |
| 2nd Author's Affiliation | Department of Electrical and Electronic Engineering Chuo University |
| Date | 1997/12/12 |
| Paper # | CPSY97-94 |
| Volume (vol) | vol.97 |
| Number (no) | 445 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |