| Presentation | 1997/10/29 Cost-Radius Balanced Plane Steiner Trees Hideki Mitsubayashi, Atsushi Takahashi, Yoji Kajitani, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Though the interconnection delay has been estimated by the function of total wire length, we cannot now ignore the effect of the path length from the source terminal to the sink terminals. Therefore we should estimate the delay by the function of both the total wire length (cost) and the source-to-sink path length (radius). In the previous paper, we proposed an algorithm which constructs a rectilinear Steiner tree which is optimized according to various balance of the cost and radius. In this paper, we propbse an algorithm which is used to modify a given rectilinear Steiner tree to reduce the cost without increasing the radius. An important feature of the algorithm is to eliminate all the existing crossings of edges. This is used as a post process for any Steiner tree algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VLSI layout / routing / delay / Steiner tree |
| Paper # | CPSY97-70 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 1997/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Cost-Radius Balanced Plane Steiner Trees |
| Sub Title (in English) | |
| Keyword(1) | VLSI layout |
| Keyword(2) | routing |
| Keyword(3) | delay |
| Keyword(4) | Steiner tree |
| 1st Author's Name | Hideki Mitsubayashi |
| 1st Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech.() |
| 2nd Author's Name | Atsushi Takahashi |
| 2nd Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. |
| 3rd Author's Name | Yoji Kajitani |
| 3rd Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. |
| Date | 1997/10/29 |
| Paper # | CPSY97-70 |
| Volume (vol) | vol.97 |
| Number (no) | 347 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |