Presentation 1997/4/25
Shared vs. Snoop : Evaluation of Cache Structure for Single-chip Multiprocessors
T. Kisuki, M. Wakabayashi, J. Yamamoto, K. Inoue, H. Amano,
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Abstract(in English) A high performance microprocessor which provides multiple instructions has been implemented on such a chip with large area. However, the performance improvement of such microprocessors will be difficult because of the limitation of instruction level parallelism. To utilize silicon resources fully, single-chip multiprocessor is proposed. In this paper, the performance of single-chip multiprocessor which has a typical bus connected multiprocessor and with a shared cache is evaluated using parallel applications from SPLASH benchmark programs. Using instruction level simulator called ISIS, snoop cache shows better performance considering the port and arbitration delay of shared cache.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) single-chip multiprocessor / cache / shared bus / performance evaluation
Paper # ICD97-8,CPSY97-8,FTS97-8
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Committee CPSY
Conference Date 1997/4/25(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Shared vs. Snoop : Evaluation of Cache Structure for Single-chip Multiprocessors
Sub Title (in English)
Keyword(1) single-chip multiprocessor
Keyword(2) cache
Keyword(3) shared bus
Keyword(4) performance evaluation
1st Author's Name T. Kisuki
1st Author's Affiliation Keio University()
2nd Author's Name M. Wakabayashi
2nd Author's Affiliation Keio University
3rd Author's Name J. Yamamoto
3rd Author's Affiliation Keio University
4th Author's Name K. Inoue
4th Author's Affiliation Keio University
5th Author's Name H. Amano
5th Author's Affiliation Keio University
Date 1997/4/25
Paper # ICD97-8,CPSY97-8,FTS97-8
Volume (vol) vol.97
Number (no) 27
Page pp.pp.-
#Pages 8
Date of Issue