Presentation 2003/4/11
A Design and Evaluation of the Performance of the CMOS Push Pull Circuit for Analog PLL Circuits
Masanoli KAWAMOTO, Fumihito IT0, Hiroshi INOUE,
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Abstract(in English) The analog PLL circuit, in which simplification of the circuit is possibly realizable by the CMOS Push Pull circuit which can obtain phase difference π. As CMOS Push Pull circuit design proposed so far, does not take especially a production process into consideration, sufficient operation and stability could not be performed. So, the design that improves a performance was assayed and the operations of the circuit were evaluated and simulated. Since the measurement and simulation are in agreement, operation and stability of the proposed PPAM circuit and the mixing effect could be obtained.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) CMOS Push Pull Circuit / Analog PLL Circuit / PPAM Circuit / Mixing / Performance Evaluation
Paper # EMD2003-3
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Committee EMD
Conference Date 2003/4/11(1days)
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Registration To Electromechanical Devices (EMD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Design and Evaluation of the Performance of the CMOS Push Pull Circuit for Analog PLL Circuits
Sub Title (in English)
Keyword(1) CMOS Push Pull Circuit
Keyword(2) Analog PLL Circuit
Keyword(3) PPAM Circuit
Keyword(4) Mixing
Keyword(5) Performance Evaluation
1st Author's Name Masanoli KAWAMOTO
1st Author's Affiliation Faculty of Engineering and Resource Science,AKITA University()
2nd Author's Name Fumihito IT0
2nd Author's Affiliation Akita Electronics Systems CO.,LTD.
3rd Author's Name Hiroshi INOUE
3rd Author's Affiliation Faculty of Engineering and Resource Science,AKITA University
Date 2003/4/11
Paper # EMD2003-3
Volume (vol) vol.103
Number (no) 15
Page pp.pp.-
#Pages 6
Date of Issue