Presentation 2004/1/19
A study for Hardware Implementation of the Neocognitron-type Image Sequence Recognition Model (Neurocomputing)
Kaname KIMURA, Sei TAKAHASHI, Hideo NAKAMURA,
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Abstract(in English) We have proposed the Neocognitron-type neural network model for discriminating image sequence, and showed the effectiveness of the proposal model by software simulation with data of image sequence. The objective of this research is to speed up identification processing by implementing the proposal model to hardware with FPGA. We designed a hardware model of the cell-circuit, which extract features of an image sequence, and we evaluated it from the viewpoint of recognition accuracy, circuit scale, operation speed. As a result, we confirmed the effectiveness of implementing this model to hardware.
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Keyword(in English) neocognitron / FPGA / digital circuit / temporal pattern recognition
Paper # NC2003-111
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Committee NC
Conference Date 2004/1/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study for Hardware Implementation of the Neocognitron-type Image Sequence Recognition Model (Neurocomputing)
Sub Title (in English)
Keyword(1) neocognitron
Keyword(2) FPGA
Keyword(3) digital circuit
Keyword(4) temporal pattern recognition
1st Author's Name Kaname KIMURA
1st Author's Affiliation Graduate School of Science and Technology, Nihon University()
2nd Author's Name Sei TAKAHASHI
2nd Author's Affiliation College of Science and Technology, Nihon University
3rd Author's Name Hideo NAKAMURA
3rd Author's Affiliation College of Science and Technology, Nihon University
Date 2004/1/19
Paper # NC2003-111
Volume (vol) vol.103
Number (no) 601
Page pp.pp.-
#Pages 6
Date of Issue