Presentation | 2004/5/12 On the Randomized Initial Point Countermeasure against Power Analysis (Part II) Tetsuya IZU, Masahiko TAKENAKA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Countermeasures against the power analysis of cryptographic applications implemented on smart cards are essential. In the case of Elliptic Curve Cryptosystems (ECC), all of the differential power analysis (DPA), the Refined Power Analysis (RPA), and the Zero-value Point Analysis (ZPA) should be considered. Itoh-Izu-Takenaka proposed the Randomized Initial Point countemeasure (RIP) satisfying high security and efficient processing speed in spite of the limitaion that it is applied only to the addition chain from the Least Significant Bit (LSB). Then, Morimoto-Mamiya-Miyaji improved RIP to apply to the addition chain from the Most Significant Bit (MSB) and the window-cased methods. However, these countermeasures are vulnerable to the address-bit DPA (ADPA). This report studies the security of RIP against ADPA, and proposes a countermeasure based on the Randomized Addressing countermeasure (RA) proposed by Itoh-Izu-Takenaka. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Smart card / Elliptic Curve Cryptosystems (ECC) / DPA / RPA / ZPA / address-bit DPA / countermeasure |
Paper # | ISEC2004-8 |
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Conference Information | |
Committee | ISEC |
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Conference Date | 2004/5/12(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Information Security (ISEC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | On the Randomized Initial Point Countermeasure against Power Analysis (Part II) |
Sub Title (in English) | |
Keyword(1) | Smart card |
Keyword(2) | Elliptic Curve Cryptosystems (ECC) |
Keyword(3) | DPA |
Keyword(4) | RPA |
Keyword(5) | ZPA |
Keyword(6) | address-bit DPA |
Keyword(7) | countermeasure |
1st Author's Name | Tetsuya IZU |
1st Author's Affiliation | FUJITSU LABORATORIES Ltd., Secure Computing Lab.,() |
2nd Author's Name | Masahiko TAKENAKA |
2nd Author's Affiliation | FUJITSU LABORATORIES Ltd., Secure Computing Lab., |
Date | 2004/5/12 |
Paper # | ISEC2004-8 |
Volume (vol) | vol.104 |
Number (no) | 53 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |