Presentation 2004-07-21
Development of DPA Evaluation Platform for 8 bit Processor
Koichi FUJISAKI, Yuki TOMOEDA, Hideyuki MIYAKE, Yuichi KOMANO, Atsushi SHIMBO, Shinichi KAWAMURA,
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Abstract(in English) A lot of papers have been published about side channel attacks, which expose a secret key in cryptographic module, using a power consumption or execution time. There is a problem that we can't evaluate threats or countermeasures of the attacks in papers, because there is no standard evaluation platform for the side channel attack. The tamper-resistance standardization research committee which established in INSTAC(Information Standardization Center) within the Japanese Standards Association(JSA), designed a standard evaluation platform with 8 bit CPU(Z80) and opens its specification to the public. This paper reports the actual experiment of DPA(Differential Power Analysis) using the standard evaluation platform(INSTAC-8).
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Keyword(in English) Side channel attack / Power analysis / Evaluation platform
Paper # ISEC2004-55
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Committee ISEC
Conference Date 2004/7/14(1days)
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Paper Information
Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of DPA Evaluation Platform for 8 bit Processor
Sub Title (in English)
Keyword(1) Side channel attack
Keyword(2) Power analysis
Keyword(3) Evaluation platform
1st Author's Name Koichi FUJISAKI
1st Author's Affiliation Toshiba, Corporate Research & Development Center()
2nd Author's Name Yuki TOMOEDA
2nd Author's Affiliation Toshiba, Social Network & Infrastructure Systems Company
3rd Author's Name Hideyuki MIYAKE
3rd Author's Affiliation Toshiba, Corporate Research & Development Center
4th Author's Name Yuichi KOMANO
4th Author's Affiliation Toshiba, Corporate Research & Development Center
5th Author's Name Atsushi SHIMBO
5th Author's Affiliation Toshiba, Corporate Research & Development Center
6th Author's Name Shinichi KAWAMURA
6th Author's Affiliation Toshiba, Corporate Research & Development Center
Date 2004-07-21
Paper # ISEC2004-55
Volume (vol) vol.104
Number (no) 200
Page pp.pp.-
#Pages 8
Date of Issue