| Presentation | 2004/3/8 A Study on the effect of cache structure to the cache timing attack for a block cipher Yoshitaka IKEDA, Toshinobu KANEKO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In 2002. Tsunoo et al. proposed a Cache Attack using a timing of CPU cache. Cache attack can be applied for cipher algorithms which have substitution boxes generally. So. Many algorithms, like CRYPTREC Proposed cipher including AES, had attacked. In the paper of Casche attack for Camellia, by Tsunoo et al. they picked up 2^<18> faster plaintexts from 2^<28> random plaintexts and using them with 2^<24> brute force search for the subkeys, they found secret key. In this paper, we report that we can attack Camellia, finding constraints of S-box inputs, with 2^<21.4> plaintexts by the average encryption speed method. We confirmed it by computer simulation, it took 22 minutes CPU time with PentiumIII 550MHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Block cipher / Cache Attack / Camellia / Average Encryption Speed Method |
| Paper # | IT2003-62,ISEC2003-102,WBS2003-180 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2004/3/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on the effect of cache structure to the cache timing attack for a block cipher |
| Sub Title (in English) | |
| Keyword(1) | Block cipher |
| Keyword(2) | Cache Attack |
| Keyword(3) | Camellia |
| Keyword(4) | Average Encryption Speed Method |
| 1st Author's Name | Yoshitaka IKEDA |
| 1st Author's Affiliation | Department of Electrical Engineering, Faculty of Engineering, Tokyo University of Science.() |
| 2nd Author's Name | Toshinobu KANEKO |
| 2nd Author's Affiliation | Department of Electrical Engineering, Faculty of Science and Technology, Tokyo University of Science. |
| Date | 2004/3/8 |
| Paper # | IT2003-62,ISEC2003-102,WBS2003-180 |
| Volume (vol) | vol.103 |
| Number (no) | 712 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |