| Presentation | 2002/12/9 A Multiple Power Analysis Attack against Side Channel Attack Countermeasure MIST Katsuyuki OKEYA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Wheras Walter has proposed MIST algorithm as a countermeasure against side channel attacks, we show that a multiple power analysis attack can detect a portion of a secret exponent. A side channel attack is an attack that takes advantage of information leaked during execution of a cryptographic procedure. MIST is an exponentiation algorithm in which moduli are randomly chosen from 2,3,5 for resisting against side channel attacks. Several paper discussed its immunity against side channel attakcs, but they did not consider a multiple power analysis. The multiple power analysis uses plural MS sequences, which are sequences of multiplications and squarings, and obtained by the distinguishability and measurements. The multiple power analysis relates the MS sequences each other, and deduces the secret exponent. In this paper, the multiple power analysis detects the value of MIST's secret exponent modulo 30. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Side channel Attacks / MIST / Multiple Power Analysis / RSA / Exponentiation |
| Paper # | ISEC2002-104 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2002/12/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multiple Power Analysis Attack against Side Channel Attack Countermeasure MIST |
| Sub Title (in English) | |
| Keyword(1) | Side channel Attacks |
| Keyword(2) | MIST |
| Keyword(3) | Multiple Power Analysis |
| Keyword(4) | RSA |
| Keyword(5) | Exponentiation |
| 1st Author's Name | Katsuyuki OKEYA |
| 1st Author's Affiliation | Hitachi, Ltd., Systems Development Laboratory() |
| Date | 2002/12/9 |
| Paper # | ISEC2002-104 |
| Volume (vol) | vol.102 |
| Number (no) | 511 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |