| Presentation | 2004-06-17 The Design of Inverse Function Delayed Neuron with the Stochastic Logic Hongge Li, Yoshihiro Hayakawa, Shigeo Sato, Koji Nakajima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we present a new digital architecture for neuron hardware that can be implemented using a field programmable gate array (FPGA). The proposed neuron provides a new neuron model of Inverse function Delayed. In order to decrease the circuit area, we employ a new architecture of inverse function with the stochastic logic. Since the property of stochastic logic, the scale of a circuit is smaller than a .conventional digital circuit. On the other hand, the stochastic logic requires the certain accumulation time for averaging. Therefore, the ID model of high-speed convergence remedy this shortcoming. The simulation experimental results show that the inverse function variance is relationship with the accumulation time, and this digital system can perform the associative memory. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Stochastic Logic / Inverse Function / ID model / FPGA |
| Paper # | NLP2004-19 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2004/6/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Design of Inverse Function Delayed Neuron with the Stochastic Logic |
| Sub Title (in English) | |
| Keyword(1) | Stochastic Logic |
| Keyword(2) | Inverse Function |
| Keyword(3) | ID model |
| Keyword(4) | FPGA |
| 1st Author's Name | Hongge Li |
| 1st Author's Affiliation | Laboratory for Brainware Systems Laboratory for Nanoelectronics and Spintronics Research Institute of Electrical Communication, Tohoku University() |
| 2nd Author's Name | Yoshihiro Hayakawa |
| 2nd Author's Affiliation | Laboratory for Brainware Systems Laboratory for Nanoelectronics and Spintronics Research Institute of Electrical Communication, Tohoku University |
| 3rd Author's Name | Shigeo Sato |
| 3rd Author's Affiliation | Laboratory for Brainware Systems Laboratory for Nanoelectronics and Spintronics Research Institute of Electrical Communication, Tohoku University |
| 4th Author's Name | Koji Nakajima |
| 4th Author's Affiliation | Laboratory for Brainware Systems Laboratory for Nanoelectronics and Spintronics Research Institute of Electrical Communication, Tohoku University |
| Date | 2004-06-17 |
| Paper # | NLP2004-19 |
| Volume (vol) | vol.104 |
| Number (no) | 112 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |