| Presentation | 2003/10/14 The design of neurochip with Inverse Delayed model Tatsuaki DENDA, Shinya SUENAGA, Yoshihiro HAYAKAWA, Koji NAKAJIMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We can realize high-speed information parallel processing by implementing the hardware of neural networks. ID model has the possibility to escape from the local minimum by using the negative resistance region given by the N-type nonlinear output inverse function. Therefore, we expect that both high performance for searching solutions of optimization problems and high-speed information processing can be realized by implementing the hardware of ID model. We design full connected neural networks with 36 neurons and 1296 synapses based on analog circuits. In this report, we describe implementation of the hardware neural networks with ID model, then check the behavior of designed neurochip by HSPICE simulations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | negative resistance region / N-type nonlinear output inverse function / neurochip / optimization problem |
| Paper # | NLP2003-91 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2003/10/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The design of neurochip with Inverse Delayed model |
| Sub Title (in English) | |
| Keyword(1) | negative resistance region |
| Keyword(2) | N-type nonlinear output inverse function |
| Keyword(3) | neurochip |
| Keyword(4) | optimization problem |
| 1st Author's Name | Tatsuaki DENDA |
| 1st Author's Affiliation | Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University() |
| 2nd Author's Name | Shinya SUENAGA |
| 2nd Author's Affiliation | Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University |
| 3rd Author's Name | Yoshihiro HAYAKAWA |
| 3rd Author's Affiliation | Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University |
| 4th Author's Name | Koji NAKAJIMA |
| 4th Author's Affiliation | Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University |
| Date | 2003/10/14 |
| Paper # | NLP2003-91 |
| Volume (vol) | vol.103 |
| Number (no) | 375 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |