| Presentation | 2003/10/17 Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's Fayez ROBERTSALIBA, Kyeong-Sik MIN, Hiroshi KAWAGUCHI, Kouichi KANDA, Takayasu SAKURAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. A test chip has been fabricated using 0.18-um triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low-voltage SRAM / low-power SRAM / row-by-row / low-leakage / leakage reduction technique / subthreshold current |
| Paper # | DSP2003-136,ICD2003-134,IE2003-96 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2003/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's |
| Sub Title (in English) | |
| Keyword(1) | Low-voltage SRAM |
| Keyword(2) | low-power SRAM |
| Keyword(3) | row-by-row |
| Keyword(4) | low-leakage |
| Keyword(5) | leakage reduction technique |
| Keyword(6) | subthreshold current |
| 1st Author's Name | Fayez ROBERTSALIBA |
| 1st Author's Affiliation | Institute of Industrial Science, University of Tokyo() |
| 2nd Author's Name | Kyeong-Sik MIN |
| 2nd Author's Affiliation | Institute of Industrial Science, University of Tokyo:School of Electrical Engineering, Kookmin University |
| 3rd Author's Name | Hiroshi KAWAGUCHI |
| 3rd Author's Affiliation | Institute of Industrial Science, University of Tokyo |
| 4th Author's Name | Kouichi KANDA |
| 4th Author's Affiliation | Institute of Industrial Science, University of Tokyo:System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| 5th Author's Name | Takayasu SAKURAI |
| 5th Author's Affiliation | Institute of Industrial Science, University of Tokyo |
| Date | 2003/10/17 |
| Paper # | DSP2003-136,ICD2003-134,IE2003-96 |
| Volume (vol) | vol.103 |
| Number (no) | 380 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |