| Presentation | 2003/10/17 Design of a Field Programmable VLSI Processor Based on Bit-Serial-Pipeline Architectures Naotaka OHSAWA, Osamu SAKAMOTO, Masanori HARIYAMA, Michitaka KAMEYAMA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a field programmable VLSI processor (FPVLSI) based on bit-serial pipeline architecture that reduces complexity of a programmable interconnection network. The direct allocation of a control/data flow graph (CDFG) is employed where only a single node in a CDFG is mapped into a single cell so that the interconnection complexity is greatly reduced. Two-dimensional mesh network and bit-serial pipeline architecture also reduces the complexity of switch blocks. The FPVLSI with 64 cells is designed in a 0.18μm CMOS design rule. The performance of the FPVLSI is evaluated to be 13 times higher than that of the conventional FPGA in a typical application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Two-dimensional mesh network / Allocation |
| Paper # | DSP2003-133,ICD2003-131,IE2003-93 |
| Date of Issue |
| Conference Information | |
| Committee | DSP |
|---|---|
| Conference Date | 2003/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a Field Programmable VLSI Processor Based on Bit-Serial-Pipeline Architectures |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Two-dimensional mesh network |
| Keyword(3) | Allocation |
| 1st Author's Name | Naotaka OHSAWA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Osamu SAKAMOTO |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Masanori HARIYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 4th Author's Name | Michitaka KAMEYAMA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2003/10/17 |
| Paper # | DSP2003-133,ICD2003-131,IE2003-93 |
| Volume (vol) | vol.103 |
| Number (no) | 380 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |