Presentation 2003/10/17
Architecture of a Recursive-Computation-Based Stereo Matching VLSI Processor
Kiyoshi MIURA, Masanori HARIYAMA, Michitake KAMEYAMA,
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Abstract(in English) High-speed correspondence matching is essential for stereo vision.A typical method for correspondence matching is one based on SAD(Sum of Absolute Differences) computation. This paper presents a stereo matching algorithm that minimizes the computational amount by re-using the intermediate results of SADs. A VLSI processor architecture is also proposed based on an optimal allocation that minimizes the complexity of the interconnection network. As a result, the performance of the VLSI processor becomes 5000 times faster than that of a general-purpose processor.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Three-Dimensional Instrumentation / Stereo Vision / Sum of Absolute Differences(SAD) / Scheduling / Allocation
Paper # DSP2003-128,ICD2003-126,IE2003-88
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Conference Information
Committee DSP
Conference Date 2003/10/17(1days)
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Paper Information
Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Architecture of a Recursive-Computation-Based Stereo Matching VLSI Processor
Sub Title (in English)
Keyword(1) Three-Dimensional Instrumentation
Keyword(2) Stereo Vision
Keyword(3) Sum of Absolute Differences(SAD)
Keyword(4) Scheduling
Keyword(5) Allocation
1st Author's Name Kiyoshi MIURA
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Masanori HARIYAMA
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Michitake KAMEYAMA
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2003/10/17
Paper # DSP2003-128,ICD2003-126,IE2003-88
Volume (vol) vol.103
Number (no) 380
Page pp.pp.-
#Pages 6
Date of Issue