| Presentation | 2003/6/20 Pipeline Stage Minimization Algorithm for Embedded Processors Masaaki ABE, Keishi SAKANUSHI, Yoshinori TAKEUCHI, Masaharu IMAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the embedded system design, application specific instruction-set processors (ASIPs) which consist of application specific instructions and hardware resources are embedded to various systems. To achieve high performance and high flexibility, the pipeline architecture is often employed in ASIPs design, and the ASIP design environment, ASIP Meister, that automatically generates HDL of ASIP from micro-operation descriptions was proposed. In this paper, the resource allocation method, that allocates resources to pipeline stages of the processor with the minimum number of stages which satisfies the given maximum delay time constraint, is proposed. The proposed method searches the resource allocation which satisfy the given maximum delay time and is the minimum number of pipeline stages for all varieties of resource allocations. Experimental results show that the proposed method minimizing the number in short time under the delay constraint, five seconds confirming effectiveness of the method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded Processor / Pipeline / Scheduling / Design Optimization / ASIP Meister |
| Paper # | DSP2003-60 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2003/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Pipeline Stage Minimization Algorithm for Embedded Processors |
| Sub Title (in English) | |
| Keyword(1) | Embedded Processor |
| Keyword(2) | Pipeline |
| Keyword(3) | Scheduling |
| Keyword(4) | Design Optimization |
| Keyword(5) | ASIP Meister |
| 1st Author's Name | Masaaki ABE |
| 1st Author's Affiliation | Department of Information Systems Engineering Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Keishi SAKANUSHI |
| 2nd Author's Affiliation | Department of Information Systems Engineering Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Yoshinori TAKEUCHI |
| 3rd Author's Affiliation | Department of Information Systems Engineering Graduate School of Information Science and Technology, Osaka University |
| 4th Author's Name | Masaharu IMAI |
| 4th Author's Affiliation | Department of Information Systems Engineering Graduate School of Information Science and Technology, Osaka University |
| Date | 2003/6/20 |
| Paper # | DSP2003-60 |
| Volume (vol) | vol.103 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |