| Presentation | 2004/2/25 Chip Interleaving for DS-CDMA with Frequency Domain Equalization in a Frequency Selective Rayleigh Fading Channel Deepshikha GARG, Fumiyuki ADACHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | DS-CDMA with frequency domain minimum mean square error (MMSE) equalization can provide much better performance than that with rake combining in a frequency selective fading channel. Chip interleaving is a form of channel interleaving that improves the DS-CDMA performance by converting the channel into a highly time selective channel. When frequency domain equalization is used, the frequency selectivity of the channel is thoroughly exploited. In this paper we apply chip interleaving to DS-CDMA with frequency domain MMSE equalization to see if the performance can be further improved. It is found that chip interleaving improves the performance for all channel conditions. In addition, chip interleaving is beneficial in the presence of turbo coding and antenna diversity as well. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Chip interleaving / DS-CDMA / frequency domain equalization / turbo coding |
| Paper # | WBS2003-88,A・P2003-281,RCS2003-304,MoMuC2003-94,MW2003-250 |
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| Conference Information | |
| Committee | AP |
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| Conference Date | 2004/2/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Antennas and Propagation (A・P) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Chip Interleaving for DS-CDMA with Frequency Domain Equalization in a Frequency Selective Rayleigh Fading Channel |
| Sub Title (in English) | |
| Keyword(1) | Chip interleaving |
| Keyword(2) | DS-CDMA |
| Keyword(3) | frequency domain equalization |
| Keyword(4) | turbo coding |
| 1st Author's Name | Deepshikha GARG |
| 1st Author's Affiliation | Department of Electrical and Communication Engineering, Tohoku University() |
| 2nd Author's Name | Fumiyuki ADACHI |
| 2nd Author's Affiliation | Department of Electrical and Communication Engineering, Tohoku University |
| Date | 2004/2/25 |
| Paper # | WBS2003-88,A・P2003-281,RCS2003-304,MoMuC2003-94,MW2003-250 |
| Volume (vol) | vol.103 |
| Number (no) | 677 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |