| Presentation | 2004/1/16 Improvement of Clock Scheduling Method in Consideration of Clock Tree Length Hajime YAMAZAKI, Atsushi TAKAHASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In order to achieve a shorter clock period by a clock tree with less wire length and less power consumption, a clustering based clock scheduling algorithm was proposed. In the algorithm, first registers are partitioned into clusters by their locations, and then clusters are modified to improve the clock period by changing the cluster to which a critical register belongs. However, in the modification of clusters, excessive modifications are carried out because critcal registers which break cycle are not identified well. In this paper, we propose a method that reduces the number of modification by identifying critical register. Critical registers are identified by extracting non trivial strongly connected components of critical constraint graph. In experiments, the validity of the enhancement is confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | semi-synchronous circuit / clock-tree / clock schedule / cluster / critical cycle |
| Paper # | VLD2003-126,CPSY2003-35 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2004/1/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improvement of Clock Scheduling Method in Consideration of Clock Tree Length |
| Sub Title (in English) | |
| Keyword(1) | semi-synchronous circuit |
| Keyword(2) | clock-tree |
| Keyword(3) | clock schedule |
| Keyword(4) | cluster |
| Keyword(5) | critical cycle |
| 1st Author's Name | Hajime YAMAZAKI |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Atsushi TAKAHASHI |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| Date | 2004/1/16 |
| Paper # | VLD2003-126,CPSY2003-35 |
| Volume (vol) | vol.103 |
| Number (no) | 579 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |