Presentation 2004/1/15
Proposal of N-dimensional Fast Hadamard Transform Algorithm and Implementation on Dynamically Reconfigurable Device
Hiroaki TAKAHASHI, Junji KITAMICHI, Kenichi KURODA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose architecture of Fast Hadamard Transform (FHT), one of the orthogonal transform for digital signals. Our proposed architecture can reduce parallelism of FHT butterfly to 1/2^n dynamically. Also, we describe a design method for implementing proposed architecture on dynamically reconfigurable devices. Therefore, our FHT system has dynamical alterability of dimension, number of signals, and parallelism. This alterability enables the system to adapt itself to outside requirements changing. We implemented the architecture on a dynamically reconfigurable device PCA-1 with single parallelism. As the result of implementation and evaluation, our system has achieved higher speed performance than our previous work.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Orthogonal Transform / Fast Hadamard Transform / Dynamically Reconfigure / PCA
Paper # VLD2003-123,CPSY2003-32
Date of Issue

Conference Information
Committee VLD
Conference Date 2004/1/15(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Proposal of N-dimensional Fast Hadamard Transform Algorithm and Implementation on Dynamically Reconfigurable Device
Sub Title (in English)
Keyword(1) Orthogonal Transform
Keyword(2) Fast Hadamard Transform
Keyword(3) Dynamically Reconfigure
Keyword(4) PCA
1st Author's Name Hiroaki TAKAHASHI
1st Author's Affiliation The University of Aizu, Graduate School of Computer Science and Engineering()
2nd Author's Name Junji KITAMICHI
2nd Author's Affiliation The University of Aizu, Graduate School of Computer Science and Engineering
3rd Author's Name Kenichi KURODA
3rd Author's Affiliation The University of Aizu, Graduate School of Computer Science and Engineering
Date 2004/1/15
Paper # VLD2003-123,CPSY2003-32
Volume (vol) vol.103
Number (no) 578
Page pp.pp.-
#Pages 6
Date of Issue